Many elementary logic cells of integrated circuits, for example for forming memory arrays, are known. Such integrated elementary cells are submitted to many external disturbances, and may especially be particularly sensitive to heavy ion impacts. Such impacts generate eddy currents which, according to the impact location on the circuit, are capable of modifying the state of junctions in the semiconductor material of the integrated circuit, and thus of modifying the cell state.
FIG. 1A illustrates a conventional synchronous inverter circuit capable of being used in an elementary memory cell.
This circuit comprises a series association, between a terminal of application of a D.C. voltage Vdd and the ground, of a first and of a second P-channel transistors, p1 and p2, and of a first and of a second N-channel transistors, n3 and n4. Input terminal IN of the circuit is connected to the gates of transistors p1 and n4 and output terminal OUT of the circuit is connected to the junction point of transistors p2 and n3. The gates of transistors n3 and p2 respectively receive a clock signal CLK and its inverse.
A disadvantage of a simple cell such as in FIG. 1A is that, if a heavy ion reaches a node of the circuit and causes a switching of this node, or causes a switching of the state of a transistor, the circuit output level may be directly affected.
To ascertain that the information contained in a memory or in elementary logic cells is not modified by the external power inputs, it is known to form improved memory cells for example providing a redundancy of the stored information.
Patent EP 0 708 447, incorporated herein by reference, describes a memory cell comprising two interlaced information storage loops: the information is stored at two locations of the cell, at the level of nodes belonging to each of the two loops. If a disturbance occurs on one of the nodes, the redundancy of the memory cell structure enables to restore the information over the entire cell.
However, such a circuit requires a large number of transistors, which implies a high power consumption. Further, several heavy ion impacts could occur at the same time on the circuit at two locations close to the two information storage areas. The memory state can thus be modified.
U.S. Pat. No. 7,719,887, incorporated herein by reference, provides forming a data storage register associating two logic gates head-to-tail. A capacitive structure is provided in parallel with the two logic gates. The current to be used to switch the state of nodes of this structure is thus increased. The disadvantage of this structure is that the power required to intentionally write into the structure must also be high.
FIG. 1B illustrates a circuit known as a Schmitt trigger. This circuit comprises a series association of four transistors, p1 and p2 of type P and n3 and n4 of type N, between a terminal of application of a D.C. voltage Vdd and ground. Circuit input IN is connected to the gates of transistors p1, p2, n3, and n4 and circuit output OUT is connected to the junction point of transistors p2 and n3.
A P-type transistor, p5, is placed between the junction point of transistors p1 and p2 and ground. The gate of transistor p5 is connected to output OUT of the circuit. An N-type transistor, n6, is placed between the junction point of transistors n3 and n4 and terminal Vdd. The gate of transistor n6 is connected to output OUT of the circuit.
Transistors p5 and n6 avoid for a temporary switching of the state of a transistor, caused for example by a heavy ion impact, to modify the circuit output state. Indeed, these transistors create a loop which opposes state switchings of the circuit. However, this solution has the disadvantage that it also involves more power and write time to intentionally modify the circuit state. Such increases in consumption and delays are generally not desired.
There thus is a need for an elementary cell having a significant robustness with respect to external disturbances, and which does not require a high write power.